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Datasheet File OCR Text:

OEB
56
C1
V
SEL
28
1D
OEA
1 CE
V
1D C1
V
V
V
C1 1D
V
1 of 12 Channels
1
V
V
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PI74AVC+16268
12-Bit to 24-Bit Registered Bus Exchanger with 3-State Outputs
Product Features
PI74AVC+16268 is designed for low-voltage operation, VCC = 1.65V to 3.6V True 24mA Balanced Drive @ 3.3V IOFF supports partial power-down operation 3.6 I/O Tolerant Inputs and Outputs All outputs contain a patented DDC (Dynamic DriveControl) circuit that reduces noise without degrading propagation delay. Industrial operation: 40C to +85C Available Packages: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductors PI74AVC+ series of logic circuits are produced using the Companys advanced submicron CMOS technology, achieving industry leading speed. The PI74AVC+16268, a 12-bit to 24-bit registered bus exchanger designed for 1.65V to 3.6V VCC operation, is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower frequency bus. It provides synchronous data exchange between the two ports. Data is stored in internal registers on the lowto-high transition of the clock (CLK) input when appropriate clockenable (CLKEN) inputs are low. The select (SEL) line is synchronous with CLK and selects 1B or 2B input data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B-port. Data flow is controlled by the active-low output enables (OEA, OEB). These control terminals are registered so bus direction changes are synchronous with CLK. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE should be tied to VCC through a pullup resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. Because OE is being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse.
Logic Block Diagram
CLK CLKEN1B 29 2
CLKEN2B 27 30
CLKENA1
CLKENA2
55 C1
1D
C1 1D
23
1B1
G1 1 A1 8 1
CE C1 1D 6
2B1
CE
CE C1 1D CE C1 1D
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PI74AVC+16268 12-Bit to 24-Bit Registered Bus Exchanger w/3-State Outputs
Pin Description
Pin Name OE CLK SEL CLK EN A,1B,2B GND VCC D e s cription O utput Enable Input (Active LO W) Clock Select (Active Low) Clock Enable (Active Low) 3- State O utputs Ground Power
(1)
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 56-Pin 14 A, K 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
OEA CLKEN1B 2B3 GND 2B2 2B1 VCC A1 A2 A3
OEB CLKENA2 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 CLKENA1 CLK
Truth Tables
Output Enable
CLK
Inputs OEA H H L L OEB H L H L A Z Z
Outputs 1B,2B Z Active Z Active
Outputs 1B 2B 1B0(2) 2B0(3) L(2) X H(2) X X L X H
GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 CLKEN2B SEL
Active Active
A to B STORAGE (OEB = L) Inputs CLKENA1 CLKENA2 H H L L L L X L X L B to A STORAGE (OEA = L)
Inputs CLKEN1B H X L L X X
CLK X
A X L H L H
CLKEN2B CLK SEL 1B X H X X L L X X H L H H L L X X L H X X
2B X X X X L H
Outputs A A0(3) A0(3) L H L H
Notes: 1. H = High Signal Level, L = Low Signal Level, X = Irrelevant, Z = High Impedance, = Transition, Low to High 2. Two CLK edges are needed to propagate data 3. Output level before indicated steady state input conditions were established.
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PI74AVC+16268 12-Bit to 24-Bit Registered Bus Exchanger w/3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC .............................. 0.5V to +4.6V Input voltage range, VI .................................... 0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ....... 0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) .......................... 0.5V to VCC +0.5V Input clamp current, IIK (VI <0) .................................... 50mA Output clamp current, IOK (VO <0) ............................... 50mA Continuous output current, IO ..................................... 50mA Continuous current through each VCC or GND .......... 100mA Package thermal impedance, JA(3): package A ......... 64C/W package K .................48C/W Storage Temperature range, Tstg ..................... 65C to 150C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1. Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions(1)
M in. VCC VIH Supply Voltage High- level Input Voltage Operating Data retention only VCC = 1.2V VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VIL Low- level Input Voltage VCC = 1.2V VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VI VO IOH Input Voltage Output Voltage High- level output current Active State 3- State VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V IOL Low- level output current VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V tv Input transition rise or fall rate TA Operating free- air temperature VCC = 1.65V to 3.6V 40 0 0 0 1.65 1.2 VCC 0.65 x VCC 1.7 2 GND 0.35 x VCC 0.7 0.8 3.6 VCC 3.6 6 12 24 6 12 24 5 85 ns/V C mA V M ax. 3.6 Units
Notes: 1. All unused inputs must be held at VCC or GND to ensure proper device operation.
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PI74AVC+16268 12-Bit to 24-Bit Registered Bus Exchanger w/3-State Outputs
DC Electrical Characteristics (Over the Operating Range, TA = 40C +85C)
Parame te rs VOH IOH = 6mA IOH = 12mA IOH = 24mA VOL IOL = 100A IOL = 6mA IOL = 12mA IOL = 24mA II IOFF IOZ ICC CI Control Inputs Data Inputs CO Outputs VO = VCC or GND Control Inputs VI = VCC or GND VI or VO = 3.6V VI = VCC or GND VO = VCC or GND VI = VCC or GND IO = 0 VIH = 0.57V VIH = 0.7V VIH = 0.8V Te s t Conditions (1) IOH = 100A VIH = 1.07V VIH = 1.7V VIH = 2V VCC 1.65V to 3.6V 1.65V 2.3V 3V 1.65V to 3.6V 1.65V 2.3V 3V 3.6V 0 3.6V 3.6V 2.5V 3.3V 2.5V 3.3V 2.5V 3.3V
Note: 1. Typical values are measured at TA = 25C.
M in. VCC 0.2V 1.2 1.75 2.0
M ax.
Units
0.2 0.45 0.55 0.8 2.5 10 10 40 4 4 6 6 8 8
V
A
pF
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PI74AVC+16268 12-Bit to 24-Bit Registered Bus Exchanger w/3-State Outputs
Timing Requirements (Over Operating Range)
VCC = 1.2V Parame te rs fCLOCK tW Clock frequency Pulse duration, CLK high or low Setup time A data before CLK B data before CLK SEL before CLK CLKENA1 or CLKENA2 before CLK CLKENB1 or CLKENB2 before CLK OE before CLK tH Hold time A data after CLK B data after CLK SEL after CLK CLKENA1 or CLKENA2 after CLK CLKENB1 or CLKEB2 after CLK OE after CLK 2.2 1.6 2.0 3.2 2.2 1.5 1.8 2.2 3 2.0 1.5 1.5 2.0 De s cription VCC = 1.5V 0.1V VCC = 1.8V 0.15V VCC = 2.5V 0.2V M ax. 180 VCC = 3.3V 0.3V M in. M ax. Units 180 MHz
M in. M ax. M in. M ax. M in. M ax. M in. 150
3 1.5 1.0 1.3 1.8
3 1.5 0.8 1.1 1.7
tSU
3.2 3.2 0.5 1.0 1.4 0
2.4 2.5 0.5 1.0 1.4 0
2.0 2.2 0.2 1.0 1.0 0.2
1.8 2.2 0.2 1.0 1.0 0.6
1.7 2.0 0.1 1.0 0.8 0.6
ns
0 0
0 0.2
0.1 0.2
0.6 0.5
0.6 0.5
Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
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PI74AVC+16268 12-Bit to 24-Bit Registered Bus Exchanger w/3-State Outputs
Switching Characteristics (Over Operating Range)
Parame te r fmax tpd CLK B A(1B) B(2B) A(SEL) ten tdis ten tdis CLK B B A A 8.1 9.0 8.0 9.3 9.3 9.0 9.0 8.8 5.0 5.5 5.5 6.5 6.4 7.0 6.5 6.3 From (Input) To (Output) VCC = 1.2V Typical VCC = 1.5V 0.1V M in. VCC = 1.8V 0.15V M ax. 4.8 5.0 5.0 5.4 5.8 6.0 5.5 5.5 150 2.0 2.1 2.1 2.5 2.8 3.0 2.1 2.3 VCC = 2.5V 0.2V M in. 180 1.8 1.7 1.8 2.4 2.6 2.5 1.8 2.1 4.0 4.2 4.3 4.3 4.4 3.8 4.2 3.5 M ax. VCC = 3.3V 0.3V M in. 180 1.3 1.2 1.3 1.7 1.8 1.8 1.3 1.5 3.1 3.4 3.4 3.6 3.8 3.8 3.6 3.8 ns M ax. MHz Units
M ax. M in.
Notes: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, TA= 25C
Parame te rs Outputs Enabled Outputs Disabled Te s t Conditions VCC = 1.8V 0.15V Typical Cpd Power Dissipation Capacitance CL = 0pF, f = 10 MHz 60 40 VCC = 2.5V 0.2V Typical 65 45 VCC = 3.3V 0.3V Typical 76 pF 55 Units
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PI74AVC+16268 12-Bit to 24-Bit Registered Bus Exchanger w/3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 1.2V and 1.5V 0.1V
2xVCC From Output Under Test CL = 15pF
(See Note A)
2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 O pen 2 x VCC GND
2
Load Circuit
VCC Timing Input VCC/2 0V tsu th
tW VCC Input VCC/2 VCC/2 0V
VCC
Data Input
VCC/2
VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VOL +0.1V tPHZ VCC/2 VOH -0.1V VOH 0V VOL VCC/2 0V tPLZ VCC
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
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PI74AVC+16268 12-Bit to 24-Bit Registered Bus Exchanger w/3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 1.8V 0.15V
2xVCC From Output Under Test CL = 30 15pF
(See Note A)
1 k 2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 O pen 2 x VCC GND
2k 1
Load Circuit
VCC Timing Input VCC/2 0V tsu th
tW VCC Input VCC/2 VCC/2 0V
VCC
Data Input
VCC/2
VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VCC/2 0V tPLZ VCC VOL +0.1V 0.15V tPHZ VCC/2 VOH -0.1V 0.15V VOH 0V VOL
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
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PI74AVC+16268 12-Bit to 24-Bit Registered Bus Exchanger w/3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 2.5V 0.2V
2xVCC From Output Under Test CL =30 15pF
(See Note A)
500 2 500 2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 O pen 2 x VCC GND
Load Circuit
VCC Timing Input VCC/2 0V tsu th
tW VCC Input VCC/2 VCC/2 0V
VCC
Data Input
VCC/2
VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VOL +0.15V tPHZ VCC/2 VOH -0.15V VOH 0V VOL VCC/2 0V tPLZ VCC
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 3. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
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PI74AVC+16268 12-Bit to 24-Bit Registered Bus Exchanger w/3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 3.3V 0.3V
2xVCC From Output Under Test CL = 30 15pF
(See Note A)
500 2 500 2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 O pen 2 x VCC GND
Load Circuit
VCC Timing Input VCC/2 0V tsu th
tW VCC Input VCC/2 VCC/2 0V
VCC
Data Input
VCC/2
VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VCC/2 0V tPLZ VCC VOL +0.1V 0.3V tPHZ VCC/2 VOH -0.1V 0.3V VOH 0V VOL
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
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PI74AVC+16268 12-Bit to 24-Bit Registered Bus Exchanger w/3-State Outputs
56-pin TSSOP (A) Package
56
.236 .244
6.0 6.2
1
.547 .555
13.9 14.1 1.20 .047 Max. SEATING PLANE
.004 0.09 .008 0.20 0.45 .018 0.75 .030 .319 BSC 8.1
.0197 BSC 0.50 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
.007 .011 0.17 0.27
.002 .006 0.05 0.15
56-pin TVSOP (K) Package
56
.169 .177
4.30 4.50
0.09 0.20 .0035 .008
1 .031 .041 0.80 1.05
0.45 .018 0.75 .030 .252 BSC 6.4 SEATING PLANE .047 1.20 Max.
.441 .449
11.20 11.40
.016 BSC 0.40 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS
.005 .009 0.13 0.23
.002 .006 0.05 0.15
Ordering Information
Orde ring D ata PI74AVC+16268A PI74AVC+16268K D e s cription 56- pin, 240 mil wide plastic TSSO P 56- pin, 173 mil wide plastic TVSO P
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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